18 May 2026

PistormX 500 DIP — Affordable SRAM Swap and Custom CPLD Build

Build log of my PistormX 500 DIP: hunting down an affordable replacement for the rare CY62177ESL SRAM, programming the Xilinx CPLD straight from a Raspberry Pi, and the battle to get Xilinx ISE 14.7 running on a modern Windows 11 laptop.

PistormX 500 DIP — Affordable SRAM Swap and Custom CPLD Build

The PistormX 500 DIP is a variant of Claude Schwarz' original PiStorm, adapted by FLACO for the Amiga 500 with a DIP-socketed 68000 CPU. The board uses a Raspberry Pi as an emulated 68040 and a Xilinx CPLD as bus glue, with an optional 2 MB or 4 MB SRAM chip as Fast RAM. Sounds simple — it wasn't.

1. The problem: an unaffordable RAM chip

The original design uses a CY62177ESL-55ZXI (2M × 16, 4 MB SRAM in TSOP-I-48). The schematic notes even say:

"PCB ready for CY62177ESL however due to the price of this chip only CY62167ELL are tested. Stay away from low voltage versions of this chip."

By 2026 both chips are barely available, and when you can find them you're looking at €25 or more per piece. That clashes hard with "it's a hobby project". I had some M11B416256A EDO-DRAM SOJ-40 chips lying around, but those are 5 V (the CPLD is 3.3 V with 5 V-tolerant inputs — outputs are not), too small in capacity, and would require a new PCB layout.

2. The replacement: IS61WV102416BLL-10TLI

After cross-referencing datasheets the ISSI IS61WV102416BLL-10TLI turned out to be a 1:1 drop-in alternative:

  • Same footprint: TSOP-I-48 (JEDEC MO-142)
  • Same pinout: 1M × 16, async SRAM with OE/WE/CE/UB/LB control
  • Supply: 2.4–3.6 V (compatible with the PistormX 3.3 V rail)
  • 10 ns access time (well within what the CPLD generates)
  • Capacity: 2 MB (half of the CY62177, but matches the stock firmware exactly)
  • LCSC price (part C28124): ~€8.50 — less than half of DigiKey

A 4 MB variant (IS61WV204816BLL-10TLI) exists as well, but it was around €25 at order time — not worth it for the extra 2 MB. On top of that, ram_autoconfig.v is already set to 2 MB by default:

'h01: autoconfig_f = 4'b0110; // $02 : 0110 for 2MB, 0111 for 4MB

So the 2 MB part is literally plug-and-play with the existing firmware. For a 4 MB build you'd flip that line to 4'b0111 and re-synthesize.

3. Picking a CPLD programming method

The board has a Xilinx XC95144XL-TQ100 CPLD that needs to be programmed before it does anything useful. Tracing the schematic showed that all four JTAG signals are wired straight to free Pi GPIOs, in addition to a separate PROG header (J3). Mapping the net labels in PistormX500.kicad_sch gives:

JTAG signalRaspberry Pi GPIOHeader pin TDIGPIO2713 TMSGPIO2418 TDOGPIO2522 TCKGPIO2637

Which means: no external JTAG programmer needed. The same Pi that will later emulate the 68000 can flash the CPLD over the same header. One command, no extra hardware, no flying wires.

4. Tweaking the Verilog — testing without the SRAM first

The SRAM chip still had to be ordered, but the CPLD was already in hand. To validate the soldering and JTAG chain without the board crashing, I flipped a define flag in pistormx500.v:

// `define RAM_AUTOCONFIG 1 `define RAM_NONE 1

This activates an alternative code block that hard-forces all RAM-related outputs (RAMCE, _configout, ram_dtack_range, ram_d_OE) to 0 and skips the ram_autoconfig module entirely. Result: no ghost Fast RAM polluting the bus, and a bit of extra macrocell headroom inside the CPLD.

5. Toolchain hell: ISE 14.7 on Windows 11

Xilinx ISE 14.7 is the toolchain for XC9500XL CPLDs — Vivado and even PlanAhead drop support for them. Problem: ISE is from 2013, the XC9500XL flow depends on the VC++ 2008 SP1 runtime, and Windows 11 is openly hostile to that. What I tried:

  1. "ISE 14.7 for Windows 10" VM installer → demanded BIOS virtualization. That was already enabled, but Hyper-V (Docker's WSL2 backend) was claiming VT-x exclusively. → Failed.
  2. "ISE 14.7 Full Product Installation" native → requires the well-known libPortability.dll rename trick. After that the installer hung forever at 90% (WebTalk DNS call timing out). Killed it, ran the manual licensing route. Turned out the VC++ 2008 runtime registration was broken: even xst -help hung silently. Reinstalling VC++ 2008 SP1 from Microsoft made no difference. → Dead end.
  3. VirtualBox 7 + ISE Linux VM, side-by-side with Docker → using the Windows Hypervisor Platform coexistence mode. Works. Docker kept running, VirtualBox 7 piggybacked on the same Hyper-V backend. → Success.

Lesson for anyone else hitting this: on a modern Windows 11 box that also runs Docker, the VM route is by far the least painful. ISE's VC++ 2008 runtime detection on Win11 is simply broken, no matter how many times you reinstall the redistributables. Inside a clean Linux VM it just works.

6. Running the build

Inside the Linux VM the flow is exactly what Xilinx intended back in 2013:

  1. Project Navigator → New Project → target XC95144XL-10-TQ100
  2. Add sources: pistormx500.v, ram_autoconfig.v, pistormx500.ucf
  3. Synthesize - XST → green, with only the expected "unused signal" warnings (exactly the ones RAM_NONE should produce)
  4. Implement Design → Translate + Fit → green
  5. Generate Programming File → pistormx500.jed
  6. iMPACT → Boundary Scan → Output → Create XSVF File → Add Device using the .jed → Program with Erase+Verify → Stop Writing → done

Result: a fresh pistormx500.xsvf of about 80 KB, dropped straight into my Windows working folder via the shared folder.

7. Flashing through the Pi

With the Pi mounted on J2 and the board powered, the flash procedure is two commands:

# install xc3sprog sudo apt install -y xc3sprog # cable definition matching the PistormX wiring echo 'CABLE "pistormx" GPIO TDI="27" TMS="24" TDO="25" TCK="26"' > pistormx.cable # flash sudo xc3sprog -c gpiolibgpiod -p 0 -L pistormx500.xsvf

Expected output: IDCODE 0x59604093 (the XC95144XL signature), followed by "Erasing… Programming… Verifying… Success". The CPLD stores the bitstream in EEPROM, so the Pi never needs to do this again after the first run.

8. What I learned

  • Carefully cross-referencing datasheets of obsolete parts pays off — a €25 chip sometimes has an €8.50 equivalent in a slightly different product line.
  • Using a Pi as a JTAG programmer is an underused trick. As long as the signals land on free GPIOs it's just xc3sprog and you're done.
  • ISE 14.7 on Windows 11 is not a sensible target unless you have a lot of patience. The VM route with a shared folder is the sane default.
  • Verilog `define flags are a clean way to disable subsystems for partial-board testing without forking the code.

References

Status: CPLD firmware built and ready. SRAM ordered. Hardware flash and first boot test coming up as soon as the PCB is fully populated.